2011 DVCon: Optimizing Area and Power Using Formal Methods

At DVCon 2011, a paper presented by Freescale and Cadence described a truly novel application of formal technology for something completely different than assertion-based verification (ABV). Specifically, the authors used formal engines to optimize the selection of complex (read, "higher in area & power consumption") vs. simple (read, "lower power, lower area") power control flip-flops. In this short video, one of the authors -- Team Verify's Chris Komar of the Formal Product Expert team -- elaborates in this video.


So you can quickly track it down once the DVCon 2011 proceedings are published, here is the paper's citation:
Title: "Optimizing Area and Power Using Formal Methods"
Paper 7.2 in the "Low Power Verification" session
Presented at DVCon 2011 on Wednesday March 2, 2011
Authors: Alan Carlin, Freescale Semicondutor, Inc.; Chris Komar, Cadence Design Systems, Inc.; Anuj Singhania, Freescale Semicondutor, Inc.

Category:

Science & Technology

Tags:

• 2011
• DVCon
• Chris Komar
• interview
• Freescale
• Cadence
• low power
• formal
• ABV
• verification
• EDA