The Synaptic Processing Unit

This is a video of experimental hardware - The Synaptic Processing Unit, an FPGA implementing 8k Binary Cascade Synapses (Fusi et. al.) feeding into an aVLSI IFWTA Neuron Chip, forming one coherent Neural System (In this case, one output neuron sourcing from 256 input synapses) through an AER bus. The output Neuron receives a poisson input to all its randomly uniformly potentiated or depressed synapses. Here, the top trace is the membrane potential of the IF Neuron, the bottom trace are the spikes that the neuron receives from its synapses (i.e. a 'masked' version of the original input, since some synapses are depressed and do not forward spikes). Plasticity/Learning is implemented using a novel learning rule we call STADP (Spike Timing and Activity Dependent Plasticity). In this video, the input stimuli are collectively strong enough to continuousely activate the output neuron, and more synapses will become potentiated, gradually. This is reflected in the increase of the output neuron's firing rate

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Tags:

• artificiallife
• SPU
• neuron
• synapse
• integrate
• fire
• artificial
• neural
• network
• stadp
• plasticity
• learning
• analog
• vlsi
• fpga

[ntujj]

as a electrophysiological researcher, neither can i understand it@@

[petersedin]

wow it sounds like it`s talking!

[RhythmDroid]

I don't understand this stuff, but it is artistically inspiring for me! = )