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Lecture 10 Parity Generator And Display Decoder

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Uploaded by on Dec 17, 2007

Lecture series on Digital Circuits & Systems by Prof. S. Srinivasan,
Department of Electrical Engineering, IIT Madras
For more details on NPTEL visit http://nptel.iitm.ac.in

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Top Comments

  • This is about even parity generator, not an odd bit parity generator. The p column in his table is supposed to be reversed for odd bit parity generator.

  • Awesome......wish i could attened ur classes in IIT.

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All Comments (8)

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  • Thank you very much for posting these videos! they are very helpful! This prof is so good!!!

  • Lovely stuff, this is well kool, his teaching is beyond excellent, and the video quality is very good as well, all in all awesome.

    thanx from LIBYA

  • Hello from australia! these are great!!! thanks!!

  • perfectly explained :) thanks for the explanation greetings from poland

  • Great! India's reply to MIT OCW.. good to see so many high quality universities coming out to help students by freely donating their materials.

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