Wired Communication between FPGAs

This was my excuse for a senior design project. It's an implementation of the KeeLoq cipher implemented on Xilinx Spartan-3 FPGAs programmed in VHDL. One is acting as an encoder, while the other is acting as a decoder. They're communicating through two wires. One is for serial data and the other is for the syncing clock. There's a third wire for ground. The KeeLoq cipher is used for remote keyless entry systems in cars. Mine differs from the real life remote keyless entry systems in that it's missing a few key functions. First of all, it's not wireless. Secondly, you can see me sort of implementing the incrementing plaintext. Sure, it's incrementing but the decoder isn't really checking anything. Normally, it would check the plaintext against the last plaintext. Those are the only obvious flaws I can think of so far. Anyways, special thanks to those who helped me on this thing.

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[ziljin]

I am not going to pretend I understand what that does. But looks cool.