This is a demonstration of my newly expanded 3 Bit Overlay Adder I created in Minecraft.
Shortly after completion of the 3 Bit Adder I became frustrated with it's massive size, so I took to RedstoneSim. I did some serious optimization to the footprint, and computation time.
The old footprint was 23 x 19 m2, with a massive height of 6m for 1 bit.
The new footprint is 23x 21 m2 , with a height of 3m for 2 bits.
The new 2 bit design shaved 1/3rd of a second on the C pipe's computation time (1/6th per bit).
All in it's pretty awesome to be learning and applying all this cool stuff, especially since it is actually applicable to real circuit design theory (gate wise).
Also, I address my mistake at 1:00 where I state "111 = 6" when actually "111 = 7" and the carryover is always 1.
@TheCardGuy521
I posted this video for demonstration of logic gates in minecraft, not on the attractiveness of the texture pack I use.
michamus 1 year ago
OMG!!!ugly texture pack
TheCardGuy521 1 year ago