by Joe Hupcey III 465 views
DVCon 2012 is focused on functional verification methodologies. Hence, in this video I put 2 competing methodologies to the test: a Lego Mindstorms robot programmed by Incisive Formal Verifier to solve a Rubik's cube, vs. a human speed cuber. Will man or machine prevail? See the video to find out ...
Robot design by Hans Andersson, http://tiltedtwister.com/
Incisive Formal Verifier interface: Apurva Kalia, Suman Ray, Cadence Design Systems, Inc.
by Joe Hupcey III 116 views
Cadence Senior Application Engineer Justin Sprague talks about his DVCon 2012 paper "Yikes! Why is My SystemVerilog Testbench so Slooooow?" Unbeknownst to Jason when we shot this interview, the paper went on won honorable mention! It's posted in the DVCon proceedings here: http://events.dvcon.org/events/proceedings.aspx?id=131-4
by Joe Hupcey III 152 views
Several years in the making, DVCon 2012 saw the public unveiling of the Unified Coverage Interoperability Standard ("UCIS"). In a nutshell, UCIS is a new Accellera standard for an application programming interface (API) that facilitates the interoperability of coverage data across multiple tools from multiple vendors. In this interview, John Brennan -- Cadence's rep. on the UCIS committee -- describes why this new standard is so important for users and EDA vendors alike.
by Joe Hupcey III 127 views
In this interview Adam Sherer introduces a new book on "Advanced Verification Topics" that uses UVM as a framework for functional verification with mixed-signal, multiple languages, low power, metric-driven verification, and more. The book is available on Amazon.com: http://is.gd/nTny2P and direct from the publisher LULU http://www.lulu.com/product/paperback/advanced-verification-
by Joe Hupcey III 219 views
At DVCon 2012, long time Cadence Connections Partner AMIQ launch new product -- the "Verissimo" SystemVerilog testbench linter is optimized for functional verification with UVM, and supports users adding their own custom rules. In this video AMIQ's CEO Cristian Amitroaie reviews the highlights of this exciting new offering. More details on Verissimo is posted here: http://www.dvteclipse.com/datasheet/Verissimo_SystemVerilog_
by Joe Hupcey III 105 views
In this interview on the floor of DVCon 2012, NextOp CEO shares the latest news on how customers are applying assertion synthesis for spec verification as much as dynamic and formal assertion-based verification. Yunshan also gives a preview of the DVCon tutorial, "Using 'Apps' to Take Formal Analysis Mainstream", http://dvcon.org/eventdetails?id=131-5-T More on NextOp and their flagship product, BugScope: http://www.nextopsoftware.com/
by Joe Hupcey III 184 views
In this interview Product Engineer Chris Komar recaps the tutorial on formal apps -- including the gist of the app methodology and some examples. More background on this event is available in the original DVCon abstract http://dvcon.org/eventdetails?id=131-5-T and in this article by Richard Goering: http://is.gd/1CgIOB
by Joe Hupcey III 66 views
In this interview Pete Hardee, the moderator of the DVCon 2012 panel "Earn Your Degree in the Low-Power Arts and Sciences", recaps the highlights of this forum. (For a written report on this panel, consult Richard Goering's Industry Insights article "DVCon User Panelists: Is Low Power Design Worth the Costs?" http://is.gd/nulthk )
by Joe Hupcey III 206 views
Don O'Riordan, Sr. Architect in Virtuoso R&D, shares some background information on his DVCon 2012 paper, "PSL/SVA Assertions In SPICE". (Wait, aren't PSL and SVA digital verification languages? Please let Don explain ...)
Link to the proceedings entry: http://events.dvcon.org/events/proceedings.aspx?id=131-1-P
Full paper citation:
1P.2 PSL/SVA Assertions In Spice
Speaker: Donald J. O'Riordan - Cadence Design Systems, Inc.
Authors: Donald J. O'Riordan - Cadence Design Systems, Inc.
Prabal K. Bhattacharya - Cadence Design Systems, Inc.
by Joe Hupcey III 71 views
In this video Cadence's Frank Schirrmeister recaps the highlights of the DVCon 2012 panel titled, "Build or Buy: Which is the Best Practice for Hardware-Assisted Verification?"
Update: here is Richard Goering's detailed report on this panel: http://is.gd/lZ56Lk
Original event abstract: http://dvcon.org/eventdetails?id=131-120
by Joe Hupcey III 183 views
In this interview at DVCon 2012, Vigyan Singhal of Oski Technology announces a truly unique challenge -- they pledge to take a sight-unseen design and produce meaningful results for the challenger within the 72 hours of DAC. I've never heard of anything quite like this in the EDA industry, so I'm personally excited to see how it works out. More info here: http://www.oskitech.com/challenge/
by Joe Hupcey III 219 views
In this interview Neyaz Khan of Maxim Semiconductor reviews the highlights of his paper, "From Spec to Verification Closure: A Case Study of Applying UVM-MS for First Pass Success to a Complex Mixed-Signal SoC Design". The full paper is archived in the conference proceedings here: http://events.dvcon.org/events/proceedings.aspx?id=131-6
by Joe Hupcey III 78 views
In this interview, Rob Meyer of Medtronic talks about his DVCon 2012 paper, "Creating a Complete Low Power Verification Strategy Using the Common Power Format and UVM". The full paper is available in the conference proceedings here: http://events.dvcon.org/events/proceedings.aspx?id=131-1-P
by CadenceDesign 86 views
Please enjoy these highlights from this year's Design & Verification Conference (DVCon) in San Jose this past February 27 through March 1, 2012.
For a more detailed report on the conference, consider this post from Joe Hupcey III, "Photo Essay, Video Playlist, and Comments on DVCon 2012"
The conference proceedings are available here: