Home made FPGA computer

[Richie086]

Wow, amazing! Good job on this project..

[skawanagi]

This is an amazing result for a single person. I can`t imagine the tremendous effort you put into this project. Could you estimate the time needed from start to completion? Also, I would be interested in the total cost of the hardware. What was your primary goal when deciding to start with building this?

[capons1990]

@skawanagi

Hi :)

I was not realy single, a  friend has code the interface of the audio DAC, PS2 interface driver , make audio file and bitmap file.

The time from the start to the end was 1 jahr for this version. but i have make a lot of pause.

i 'm in a school and sometime an exam period coming ;)

1 jahr is long because i never have VHDL course, and i have learn C++ object oriented part with this project..

[capons1990]

@skawanagi

the cost was not the primary goal. but actualy the board cost is 279 $ for academic

If i remove the 3D part of the project , a FPGA with 20K lut is oky.

[capons1990]

@skawanagi

the cost was not the primary goal. but actualy the board cost is 279 $ for academic

If i remove the 3D part of the project , a FPGA with 20K lut is oky.

[tennirva]

(Con't)

If you write the linux's kernel too, Would you think you can write a device driver to support your "home-made graphics library" ? Both of 2D and 3D.

Another thing is that the kernel that relies on X86 architecture. I'm not quite an OS software person, so I'm not sure if it's difficult to modify just this part to support our "home made system" (CPU, BUS, etc).

[capons1990]

@tennirva

Hi, thanks for comment : D

I'm not a OS software person to, I don't know how linux work, how linux draw.

if it's possible to port graphic part on linux i have no idea.

My OS has no interruption, and no MMU, All work like a game runing in a infinite loop.

the bus system is very simple. When i have translate frome ARM9(Extern) to NIOS II(intern) , it was made fast because i don't have use a peripheral of the ARM9. All timer, SPI,Ethernet ect is in FPGA logique.

[capons1990]

@tennirva

I think use a X86 is not a problem

Ahahahah The only problem was the difference bettwin GCC for arm and GCC for NIOS II, they don't have the same idea of "What is a signed/unsigned" XD

The bus system is not a standard bus,If the processor want read something -> it read a FIFO, it was design for make possible parallel (ARM EBI) and serial control (RS232 in begin XD). but implement a bridge is not a probleme.

[tennirva]

Your project is very interesting to me. If you are capable of both coding and hardware Design, I think you could make a huge contribution to migrating the whole x86 Linux onto the FPGA. All I have seen in public, there are many FPGA-Based Linux but none (or few all them, in case I don't know) has a significant Graphics that supports daily-life applications (For example, Internet Browsers, Office, etc)

(to be continued)...

[jansendup]

Wow, amazing! How long have you been working on it? Did you even design the microprocessor yourself? Still a student or working already?

[capons1990]

@jansendup

I have make this in my hobbies time 1 years :)

No the microprocessor is a nios II but the GPU, memory controller, and all other think are home made ;)

35'000 line of VHDL code, 40'000 line of C++ code

I studing ;)

[jansendup]

@capons1990 Wow, that is just so AWESOME! So you basically started designing this at the same age I'm now. Where do you study? I'm trying something similar, (A lot simpler though) on the DE0 dev board. Just started so still can't decide what memory I'm gonna use for the GPU and where to store the active image being displayed. Was thinking to maybe store the active image on the SDRAM and then create memory on the FPGA for the GPU... How did you do it?

[capons1990]

@jansendup

I studie in a HES-SO in swisszerland.

In me designe i have make a sdram controller with a generic number of access port. like this :

[capons1990]

Every thing use the sdram to store data.

GPU texture, GPU frame, VGA frame, GPU stack of instruction, CPU code, CPU data, ethernet virtual fifo are to in the sdram.

And RAM internal of FPGA are only used in fifo mode to Pipline all. as possible. and incrase performance

[jansendup]

@capons1990 What year of study? Lol, are you extra smart there or are the standards really high there?

[capons1990]

@jansendup

i have make this project the first year of studie in the hes-so.

Before that i have make a learning electronics in the EMVS. emvs is a school begin at 15 jahrs old.

In me school i'm not the standards, my mark of the third semester is 58/60 :p

[capons1990]

@jansendup

the unified memory map has a lot of adventage. and the sdram is very big : D

but for a first version, make a lot of small memory independante -> why not.

Ahhh just,my the sdram controller is like this:

A standar sdram controller, connected to a multiplexer with NAccesPortNumber of Command fifo (read request or write)

And NAccesPortNumber of read fifo to get the result of each read request

Sorry for bad english XD

Good luck : D

[jansendup]

@capons1990 So would you have a little bit of fifo memory on the fpga and every time a component needs to access the memory its command will be pushed on the stack as well as its line number to be selected by the multiplexer.

[jansendup]

The controller will then handle each request and then notify the component when it handles its request via the multiplexer. So if the controller is busy with another memory request will the component just wait until its done? Haha, its fine. English is not my first language as well. Thanks for the tips. Helps alot :D

[jansendup]

@jansendup What burst size did you use for the SDRAM?

[capons1990]

@jansendup

Ahhhhh

Do you implement the SDRAM controller your self ?

do you have see all bad think with SDRAM can affect bandwidth ?

Switch bettwin read and write -> bad

random access -> bad

refresh cycle of sdram -> bad

It has affraid me at first time. but finaly the sdram give to me mybe 450-420 MB/s of data (500 MB/s maximal possible with clock)

[jansendup]

@correction Not "stack", actualy ment queue ;)

[capons1990]

@jansendup

hmmmm Think all you design with great memory access latency ~ 2us or more ^^

Pipline all is the solution with high latency.

The bigest probleme with latency is the VGA generator, when 2 screen run each at 1280*1024 @ 60 hz XD

That need 314 MB/s of bandwith XD and my sdram has just 500 MB/s max.

The burst size in my design is 1 ^^ -> no burst.

héhé yes queue is better ^^

[capons1990]

@jansendup

Hmmm yes, (sorry me english is bad meby i miss all word of the answer :P)

Just, each access port has one command (Write/read) stack and one read_data stack.

in me desigh the size of fifo is 128 command and 128 read.

Each access port cost 3 embeded memory block (32 bit access)

this solution can be the more performant for a GPU design.

[drunken1079]

awesome! very nice work

[wickedtothemisty]

how are you implementing the GUI?

[capons1990]

@wickedtothemisty

The GUI is home made :) (C++)

The data structure used for store the hierarchy is a style of linked list.

Every component has : Component *next,*before; Component *kind,*parent;

and a lot of virtual function ;)

[seb2020]

wouah