Xilinx EDK Tutorial - Sharing BRAM between Hardware and Software

[ctfysh]

Thanks for the useful tutorial. Still, I have a question: If the Shared_Bram is desinged as a FIFO between ISE module and EDK module, then how can I know which address (between base_adrress and higher_address in Shared_Bram_Controller) to access using the APIs like xio_in?

[SILICAMarcom]

@ctfysh The Shared BRAM could be modified to be a FIFO, but this would require some manual editing of the HDL code. In these circumstances a single address would probably be used rather than the multiple addresses of RAM. The HDL would be configured to always present / accept the next data value at this fixed address, and the read/write control line on the FIFO could be controlled by detecting a completed bus transaction. But, if you were using MicroBlaze then you'd want to use an FSL instead!

[vorlaufable]

Thanks for the great tutorial.

With EDK 11.1 I however receive the following error:

ERROR:EDK:1555 - IPNAME:xps_bram_if_cntlr INSTANCE:shared_bram_controlle­r PARAMETER:C_SPLB_NATIVE_DWIDTH - C:\Xilinx\ISE_DS\EDK\hw\Xilinx­ProcessorIPLib\pcores\xps_bram­_if_cntlr_v1_00_b \data\xps_bram_if_cntlr_v2_1_0­.mpd line 71 - ASSIGNMENT=REQUIRE is defined in the MPD. You must specify a value in the MHS.

I made all changes to the ports in the MHS as depicted in the video. Any thoughts?

[SILICAMarcom]

@vorlaufable : As it suggests in the message, simply set the "PARAMETER C_SPLB_NATIVE_DWIDTH = 32" line in the MHS file for the BRAM controller