I'm not sure how modern chips are organized, but in my recollection registers are not part of cache. Typically, cache is just faster memory - memory that can be read from and written to. Registers can do that, but they can perform in situ operations (rotations, adds, etc).
so basicly the size of memory really depends on the register and not on the address bus. I mean it probably depends on both of them but but register is first in the hiararchy???
It's not actually a hierarchy, b/c the components have to work together, but if I understand your question, the answer is yes.
What I laid out here is a very simple case. We could have, though, just for example, a 32 bit address space with only an 8 bit bus; HOWEVER, you also then have to have a LOT more complicated control logic to marshal the 4 bytes independently.
Are A and B in like L1 cache or is that a separate thing altogether?
sloppyjoes 2 years ago
I'm not sure how modern chips are organized, but in my recollection registers are not part of cache. Typically, cache is just faster memory - memory that can be read from and written to. Registers can do that, but they can perform in situ operations (rotations, adds, etc).
TheFallibleFiend 2 years ago
Wow that is difficult to grasp... complicated but cool.
apieceoftofu 4 years ago
so basicly the size of memory really depends on the register and not on the address bus. I mean it probably depends on both of them but but register is first in the hiararchy???
darijo203 4 years ago
It's not actually a hierarchy, b/c the components have to work together, but if I understand your question, the answer is yes.
What I laid out here is a very simple case. We could have, though, just for example, a 32 bit address space with only an 8 bit bus; HOWEVER, you also then have to have a LOT more complicated control logic to marshal the 4 bytes independently.
TheFallibleFiend 4 years ago
working my way!
bender962 4 years ago