Lecture - 24 Pipelined Processor Design Basic Idea

[fckingkim]

Excuse me sir, I've noticed you are also continuously speaking. If I'm going out, I'm going out with you.

[Cdoddsy]

Well, I get none of the sound.

[Cdoddsy]

sound is missing

[SpearoWhoreo]

@Cdoddsy most of the sound comes from the right speaker

[numlook756]

ownage

[benshelly]

i almost left my own room

[napoleaninlondon]

Note that the prof has incorrectly commented on the data hazard section wherein the prof says that the I+3 also has to stall , but it does not.

[sabriath]

@napoleaninlondon : Actually he is correct. Although he states that "unless writing can be done in the front half and reading the back half of a cycle," this is just babble because there is a flipflop between the write and read side of an RF, which is used to actually sync and store the write before any further reads are done on the next cycle. Although you CAN write AND read from the same RF, the reading will always be 1 cycle too late if on the same register line.

[ckang7777]

You tell em Prof. Anshul Kumar!