In your thesis and video i see that you implement the features extraction only. Maybe since this time you realize the Haar wavelets computation for descriptor on FPGA? I try do it now on 60 fps vga. The most complex task is to calculate Haars for each interest point. That needs the neighbours values, the higher scale we have the major number of neighbours we need for orientation evaluation.
@koeficientas Yes, the Haar wavelets consume the most of the time during the software extraction of descriptors. I have in mind a design of a wavelet calculation accelerator that will utilize the 4MB SRAM on the module as a cache, but I have stopped working on this project since I lack motivation to continue - It seems to have a very little possible application area.
@banzie74 It's a SURF algorithm implementation which uses FPGA logic to accelerate the most time consuming parts of algorithm. In the example video, the calculated features are only sent into computer and displayed. I recommend reading either my thesis or at least it's extended abstract...
In your thesis and video i see that you implement the features extraction only. Maybe since this time you realize the Haar wavelets computation for descriptor on FPGA? I try do it now on 60 fps vga. The most complex task is to calculate Haars for each interest point. That needs the neighbours values, the higher scale we have the major number of neighbours we need for orientation evaluation.
koeficientas 1 month ago
@koeficientas Yes, the Haar wavelets consume the most of the time during the software extraction of descriptors. I have in mind a design of a wavelet calculation accelerator that will utilize the 4MB SRAM on the module as a cache, but I have stopped working on this project since I lack motivation to continue - It seems to have a very little possible application area.
jschvab 1 month ago
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koeficientas 1 month ago
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koeficientas 1 month ago
Good thesis.
okamiisa1 6 months ago
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koeficientas 2 months ago
Not quite clear as to what does it achieve ? What CV problem does it solve ?
banzie74 7 months ago
@banzie74 It's a SURF algorithm implementation which uses FPGA logic to accelerate the most time consuming parts of algorithm. In the example video, the calculated features are only sent into computer and displayed. I recommend reading either my thesis or at least it's extended abstract...
jschvab 7 months ago