Fairlight Xynergi Demo - Chapter 4 - Zero Latency

[bradiporitmico]

I have made some calculations and for 0,33msec latency the buffer size should be 32 sample/sec (16 stereo) @ 96KHz (as your tech details say maximum sample rate).

Yeah it's small, very small :)

[bradiporitmico]

I'm not sure on this zero latency demonstration. I mean, if you treat all the signals in a buffered way (it's digital) then you are sure that all the signals are in phase (in that particular buffer window), so you can send,return,re-effect, re-send, re-return without loose the phase: all the signals lie in the same buffer.

The buffer size could be small enough to declare it as 'zero latency' (the processor have to be very very fast) but this demonstration does not clarify the fact.

Am I wrong?