This is also a simulation, not compiling for an actual FPGA. If that's the correct terminology. I have an Altera noob board, but our chief engineer advised to just use a simulator for now.
Also, I would like to comment on the compilation process for VHDL in Quartus II. A simple FLIP-FLOP took 30s to compile. 1 single entity. I was like "woah", this is going to be a nightmare later on. Thank goodness I'm not along in thinking that, lol. I'm running a 2.8 GHz Core 2 Duo too, still took a while. I couldn't imagine this on a terrible machine. Would probably kill me.
@jandabrock Similar experience with Quartus II here with a single-XOR-gate test project (default compile settings). However, my next project, a 1300-gate NIOS II system, took maybe 10 seconds longer at most. Most of the time appears to be overhead.
For reference, I'm on an 8-core Mac Pro running Quartus II 11.0 in VMware (WinXP guest on OSX). At the time, the VM had 1 core (2.8 GHz Core 2-class Xeon) and 512 MB RAM. I've since upped the RAM since Task Manager reported a lot of swapping.
Thanks for this. I found it a good introduction for someone who knows nothing about the tools and the language. If you're still messing about with this now, maybe you can also try to do the same for the Altera Cyclone II. The board you're using is a bit pricey for hobbyist stuff, so I'm interested in the dirt-cheap open-source boards. They're selling an EP2C5T144 Altera Cyclone II board on Ebay for $47 which looks pretty interesting. I know it's a big ask for your '1.5' viewers :).
@yrofot I'm actually debating doing a miniseries on constructing a board from scratch. It only takes about $25 in parts to get going, and building a working FPGA test board from nothing would really help people familiarize with the technology.
@Tbird761 A tutorial on constructing a board from scratch would be awesome, especially if it had downloadable PCB layout. The Actel chips are cheap enough that I would have the confidence to attempt to solder one without worrying I'd stuff it up. I can solder 0.5mm pitch SMDs but I have a success rate of about 1 in 4, so I'd be concerned if the part was much more expensive.
Another thing about the Actel ProASIC3 Nano chips - it seems they don't require EEPROM, which might make the board even cheaper. Also, there are no off-the-shelf cheap dev boards from 3rd parties. You either pay Actel $99 dollars for their dev board (which has nothing much on it), or you have to make your own, whereas Altera Cyclone II boards can be had cheaply, but the component cost is quite a bit higher. Seems a bit odd, and a 'gap' in the market which could be filled by a hobbyist design!
I'm glad I was able to experience Verilog in the intro comp. engineering course I took this last semester. While the language itself is rather different from C and its offspring and seems strange syntactically (to this amateur, at least), I still enjoyed using it. Defining and building state machines with it was cool.
I seldom come across people that can teach well. Thanks to you I learned what FPGA and HDL is. Thanks for sharing.
PoirierMike 1 month ago
He looks like Sheldon
donnomar 4 months ago
This is also a simulation, not compiling for an actual FPGA. If that's the correct terminology. I have an Altera noob board, but our chief engineer advised to just use a simulator for now.
jandabrock 5 months ago
Also, I would like to comment on the compilation process for VHDL in Quartus II. A simple FLIP-FLOP took 30s to compile. 1 single entity. I was like "woah", this is going to be a nightmare later on. Thank goodness I'm not along in thinking that, lol. I'm running a 2.8 GHz Core 2 Duo too, still took a while. I couldn't imagine this on a terrible machine. Would probably kill me.
jandabrock 5 months ago
@jandabrock Similar experience with Quartus II here with a single-XOR-gate test project (default compile settings). However, my next project, a 1300-gate NIOS II system, took maybe 10 seconds longer at most. Most of the time appears to be overhead.
For reference, I'm on an 8-core Mac Pro running Quartus II 11.0 in VMware (WinXP guest on OSX). At the time, the VM had 1 core (2.8 GHz Core 2-class Xeon) and 512 MB RAM. I've since upped the RAM since Task Manager reported a lot of swapping.
joemck85 4 months ago
My company just made me the "VHDL" guy, and I know nothing about it. Still new to embedded design as it is, so, thanks for this video. :)
jandabrock 5 months ago
Thanks for this. I found it a good introduction for someone who knows nothing about the tools and the language. If you're still messing about with this now, maybe you can also try to do the same for the Altera Cyclone II. The board you're using is a bit pricey for hobbyist stuff, so I'm interested in the dirt-cheap open-source boards. They're selling an EP2C5T144 Altera Cyclone II board on Ebay for $47 which looks pretty interesting. I know it's a big ask for your '1.5' viewers :).
yrofot 8 months ago 2
@yrofot I'm actually debating doing a miniseries on constructing a board from scratch. It only takes about $25 in parts to get going, and building a working FPGA test board from nothing would really help people familiarize with the technology.
Tbird761 8 months ago
@Tbird761 A tutorial on constructing a board from scratch would be awesome, especially if it had downloadable PCB layout. The Actel chips are cheap enough that I would have the confidence to attempt to solder one without worrying I'd stuff it up. I can solder 0.5mm pitch SMDs but I have a success rate of about 1 in 4, so I'd be concerned if the part was much more expensive.
yrofot 8 months ago
Another thing about the Actel ProASIC3 Nano chips - it seems they don't require EEPROM, which might make the board even cheaper. Also, there are no off-the-shelf cheap dev boards from 3rd parties. You either pay Actel $99 dollars for their dev board (which has nothing much on it), or you have to make your own, whereas Altera Cyclone II boards can be had cheaply, but the component cost is quite a bit higher. Seems a bit odd, and a 'gap' in the market which could be filled by a hobbyist design!
yrofot 8 months ago
Comment removed
tishmcmiggins 4 months ago
I'm glad I was able to experience Verilog in the intro comp. engineering course I took this last semester. While the language itself is rather different from C and its offspring and seems strange syntactically (to this amateur, at least), I still enjoyed using it. Defining and building state machines with it was cool.
Spootmeister 1 year ago