this is an excellent and tantalising demo. Im currently using cmos 4000 logic. I would like to progress to cpld and/or fpga. What software do you use to program it? can you recommend and kits, and books to get started?
@EA78751 it is connected and haves the I/O pads. After selecting matching symbol i got no errors. I forget that part. But you didnt select it on your video, so i guess i have to do it at least one time once i have placed the I/O pads. I want to make an asynchronous with a GAL22v10, is it possible? The output Q of a JK flip flop goes to the CLK of another one and so on. I get an error on the JEDEC file that says like i have to connect all CLK to the CLKpin of the device
hey iam doing masters in telecommunication and electronics from sheffield hallam university and my professor gave me a big home to design a shematic using isp lever classic and i just started it need ur help how should i go about understanding this software ,,......waiting for your reply cheers
@bratthebombastic try this PDF Tutorial, from lattice's site "Schematic and ABEL-HDL Design Tutorial." It walks you through schematic entry. I found that Test Vectors were optional, a functional design can be made simply by adding a Schematic source, then assigning package pins with Constraint Editor, finally using the "Generate Board Level Stamp Model" process to produce a .jed file, which is what ispVM System requires to program the actual device with ispDOWNLOAD programmer hardware.
this is an excellent and tantalising demo. Im currently using cmos 4000 logic. I would like to progress to cpld and/or fpga. What software do you use to program it? can you recommend and kits, and books to get started?
firehandszarb 1 year ago
do you know what this message means? " I/O net Q2 has no pin on symbol "
0rlandissim0 1 year ago
@0rlandissim0 sounds like its not connected? or a missing I/O flag?
EA78751 1 year ago
@EA78751 it is connected and haves the I/O pads. After selecting matching symbol i got no errors. I forget that part. But you didnt select it on your video, so i guess i have to do it at least one time once i have placed the I/O pads. I want to make an asynchronous with a GAL22v10, is it possible? The output Q of a JK flip flop goes to the CLK of another one and so on. I get an error on the JEDEC file that says like i have to connect all CLK to the CLKpin of the device
0rlandissim0 1 year ago
hey iam doing masters in telecommunication and electronics from sheffield hallam university and my professor gave me a big home to design a shematic using isp lever classic and i just started it need ur help how should i go about understanding this software ,,......waiting for your reply cheers
bratthebombastic 1 year ago
@bratthebombastic
Home work*
bratthebombastic 1 year ago
@bratthebombastic try this PDF Tutorial, from lattice's site "Schematic and ABEL-HDL Design Tutorial." It walks you through schematic entry. I found that Test Vectors were optional, a functional design can be made simply by adding a Schematic source, then assigning package pins with Constraint Editor, finally using the "Generate Board Level Stamp Model" process to produce a .jed file, which is what ispVM System requires to program the actual device with ispDOWNLOAD programmer hardware.
EA78751 1 year ago
You figured that out fast! Its cool that it compiles/programs so quickly.
WoosterAudio 1 year ago
@WoosterAudio yes you may hear me shouting 'muhahaha!' and gloating with power throughout the near future.
EA78751 1 year ago
that is cool!
xmlisnotaprotocol 1 year ago