The D-Flip Flop at the end where Q bar is fed back into D produces a repetitive signal which is half the clock rate - but what is the purpose of this circuit. This is apparently something quite important and even examinable but although I know how it works, I'm not sure what the purpose is.
@KenshinsFinest It's simply a clock divider as you have identified. There are many cases where you need a clock that is some fraction of the main clock and you can use a clock divider to give you the new clock. The easiest divided clocks to create are power of 2 divisors, but any whole number divisor is reasonably easy too.
WOW.. That was amazing, thank you.. You know how long I looked at that triple "notted and" circuit for button debouncing just trying so hard to figure it out. I even asked my teacher and he wasn't quite sure.This was 20 years ago lol
14:49 You said "D started low" but D = NOT Q and there is no value at NOT Q to propagate to D which creates a long glitch. I tried it with PSPICE and didn't work. I need a little help....
@Nshuti57109: thanks so much for the comment. On the 5th rising clock edge, it looks to me like D is still high, so Q value would remain high. I know the timing diagram is a bit uneven, so maybe that threw you off.
@tarbidian : Thanks again. Though you are right. I have actually confused the Edge triggered (for FF) and Lever triggered (which is for Latches) So it now makes sense to me that since in Lever triggered Q takes the value / get copied to whatever D is within that Clock period. but when it's Edge Triggered we only consider whatever value D is only at that time and it doesn't change until the next rising/ falling clock (depend on whichever in use).
And so that's why even though in the 5th period of clock, part of D there is LOW but since we are in Edge triggered we didn't care whatever it was until the next rising Clock.
If the Clock was Level triggered were we going to change the signal for the 5th Period?
I believe there is a slightly error @ 14:03 where the clock is in the 5th period!
Shouldn't Q value have been LOW as part of D there is LOW? though it's almost unnoticeable and drawing timing diagrams is never always perfect! but you are a
Really Very good Teacher AAAAAAAA++++++++ Recomended to all students :))
thank u so much for ur brilliant video, may god bless u, keep up the good work buddy ;)
shayan22h 5 days ago
The D-Flip Flop at the end where Q bar is fed back into D produces a repetitive signal which is half the clock rate - but what is the purpose of this circuit. This is apparently something quite important and even examinable but although I know how it works, I'm not sure what the purpose is.
KenshinsFinest 1 week ago
@KenshinsFinest It's simply a clock divider as you have identified. There are many cases where you need a clock that is some fraction of the main clock and you can use a clock divider to give you the new clock. The easiest divided clocks to create are power of 2 divisors, but any whole number divisor is reasonably easy too.
tarbidian 6 days ago
This is really well explained and clear. Thanks again.
Dosalt 1 week ago
WOW.. That was amazing, thank you.. You know how long I looked at that triple "notted and" circuit for button debouncing just trying so hard to figure it out. I even asked my teacher and he wasn't quite sure.This was 20 years ago lol
mrdouble 3 weeks ago
@mrdouble I'm glad the video was a help and that you now know the secret of that debouncing circuit after 20 years :-)
tarbidian 2 weeks ago
Thanks
akshay428 1 month ago
This tutorial is amazing! So accurate, viewer friendly, and informative. Excellent diagrams too!
w7rdotblogspot 1 month ago
keep posting videos please, videos are very extremely helpful
imperialclan 3 months ago
14:49 You said "D started low" but D = NOT Q and there is no value at NOT Q to propagate to D which creates a long glitch. I tried it with PSPICE and didn't work. I need a little help....
2011bini 3 months ago
D latch: everything that happens at D input through whole period high E passes through to Q
D flip-flop: state of D passes to Q output only at rising edge of E. output of Q stays latched in between two raising edges.
Names are misleading.
koktelici 5 months ago
@Nshuti57109: thanks so much for the comment. On the 5th rising clock edge, it looks to me like D is still high, so Q value would remain high. I know the timing diagram is a bit uneven, so maybe that threw you off.
tarbidian 6 months ago
@tarbidian : Thanks again. Though you are right. I have actually confused the Edge triggered (for FF) and Lever triggered (which is for Latches) So it now makes sense to me that since in Lever triggered Q takes the value / get copied to whatever D is within that Clock period. but when it's Edge Triggered we only consider whatever value D is only at that time and it doesn't change until the next rising/ falling clock (depend on whichever in use).
so the timing diagram is an Edge Triggered aye?
Nshuti57109 6 months ago
Comment removed
Nshuti57109 6 months ago
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And so that's why even though in the 5th period of clock, part of D there is LOW but since we are in Edge triggered we didn't care whatever it was until the next rising Clock.
If the Clock was Level triggered were we going to change the signal for the 5th Period?
Cheers
Nshuti57109 6 months ago
I believe there is a slightly error @ 14:03 where the clock is in the 5th period!
Shouldn't Q value have been LOW as part of D there is LOW? though it's almost unnoticeable and drawing timing diagrams is never always perfect! but you are a
Really Very good Teacher AAAAAAAA++++++++ Recomended to all students :))
Nshuti57109 6 months ago
I came here to learn redstone. Thank you.
slthomp2 6 months ago
very very helpfull undrstood the whole concept!!
thedivyam1 9 months ago
very clear
gtN1 10 months ago
you are much better than my teacher ! :)
IzzatNadiri1992 10 months ago