Xilinx EDK Tutorial - Adding custom IP to an EDK Project - Part 2

[MrDrusev]

One issue that may be interesting to show is what if you generated a custom IP core (say a FIFO buffer) with Xilinx LogiCore and want to import that as a part of your peripheral. For me it fails for now. There should be some option that makes things work (adding the ngc file, which still doesn't work) personally I am unfortunately not aware of.

[mmsvx]

THANKS for these Great Videos and waiting for more Great ones

i am using ISE Foundation 10.1Service pack 3

which doesnt edit by itself in MPD file

so i wanted to notify the errors will occur if programmer didnt edit MPD by himself

[mmsvx]

im a student in Ain Shams Engineering University ,EGYPT

in this tutorial

u didn't make editing in MPD file which make port visible in PORT tab

and without editing it the EDK makes errors

[SILICAMarcom]

The MPD file is updated automatically when the peripheral is imported back into the Platform Studio tool. That's why we did it.

Please see part 3 of the tutorial and you'll see that the new port exists and can be connected. Thanks for watching!