IPC guidance regarding clearance space between components when designing a printed board?

[IPCAssociation]

Character limits wouldn't permit me to put my full response in one comment. If this is confusing, please follow up with me at answers(at)ipc(dot)org.

John Perry, IPC

[ajawam]

Got a question,

What happens if the circuit topology dictates a tighter spacing?

For instance, some datasheets for RF and other HS switching IC's rec. a much closer placement than the IPC spec allows? Most modern P&P can hit these tighter clearances.

[IPCAssociation]

IPC-7351A provides 3 separate land pattern geometries, coupled with 3 separate courtyard boundaries for a given surface mount component. Density Level A represents the largest of the 3, providing the most robust solder joint.  On the opposite end of the spectrum, Density Level C represents the smallest of the 3 and targets high component printed board densities.

[IPCAssociation]

If a boards circuit topology dictates even tighter spacing, the IPC-7351A Land Pattern Calculator included with the standard allows the user to further reduce the solder joint fillet goals, the courtyard boundary excess, or both, within an existing land pattern configuration. While the resulting land patterns and courtyard boundaries no longer match what has been standardized in IPC-7351A, they still follow the same mathematical model from the standard for determining land size.

[ajawam]

Thank you - I thought so. That's what I've been doing.

You Rock!!