$49 FPGA board with 500 MBytes/sec IO bandwidth

[balefrost]

I'm just an electronics beginner, but I was surprised that you wire-wrapped the daughter card to the mainboard. Would a 40 pin socket be a bad idea at those frequencies, or did you use wire-wrap for flexibility?

[ChipEnet]

@balefrost It's wire wrapped & then soldered. The 1st version didn't have the headers

but I found it didn't matter. The header & wirewrap made it easy to assemble. The

short distance is the key to making it work.

[ChipEnet]

The secret is a zoom inspection stereoscope. It lets me see the details & then

it's not so hard. I wear glasses & my hands shake without a prop. I'll do a

video on how to hand solder fine pitch SMT & BGA parts.

[narcoti]

you have some nimble fingers, even though I know how to do this, I wouldn't be able to, my hands shake too bad, I envy you.

[ChipEnet]

Stay tuned for the $29 FPGA board with 750MBytes/sec IO bandwidth

[tuxicle]

I did a board recently that needs approx. this much bandwidth (runs I/Os at 100 MHz) on a Spartan3E, but I chickened out at the last minute and made it controlled impedance (at great expense). Nice to see that just a bunch of wires performs admirably :) If you can borrow one, try looking at the signals with a FET probe rated at > 1GHz, things may not look so clean.

[soclt]

Really cool implementation! Would be awesome if the source would be open :)

[ChipEnet]

I'm not sure what you mean by the source. The board just follow the vendor's recommendation. Gb MAC is available on OpenCores. No magic here, just

an illustration.

[metallfluss]

world of warcraft download in 20 seconds :D

[ChipEnet]

Voltage translator because the FPGA is fixed at 3.3 & the PHY needs 2.5.

Program is something I wrote. Yes, I can get CRC.

[AndyKong51]

Just wonder why u need the voltage translator. I use Marvel PHY chip + Cyclone III and it can have direct connection...

What PC program do u use? You can see the CRC too? thx

BTW, I'm doing similar stuff in HK. :>

[ChipEnet]

Be sure to try your expected pin outs with a

compile before you lock in the board. Some pin

choices that looks OK can get rejected when

you do a compile & implement.

[telesniper2]

You did a really nice job on this.  I've got a board on the way and would like to do an SDR daughter card(s), in a similar fashion to the (very expensive) USRP.

[ChipEnet]

The PHYs are LSI ET1011C. Thanks.

[cordicnet]

Wow! Your approach is impressive. May I ask you what PHYs you used???

Kudos to you, sincerely.