@soclt Thank you for leaving your comment. The design works very well - no problems, no issues. I still use the technique, just a little bit improved - see my latest Altium Designer - DDR2 / DDR3 Length Matching video. And yes, I did length match diff pairs.
Simulations: I have done couple of simulations before and ... from my experience, when you follow design guide rules, you don't need to simulate. I have seen some boards what passed simulation and failed in reality. On other hand, I have not seen any boards what followed design guides and failed - they all worked very well. Therefore, I believe the simulation is necessary only in cases where you can't follow design guide.
Impedance: I usually start with routing everything (except powers) by 0.1mm / 0.1mm (track width / gap). When I am approximately in middle of layout, I ask PCB manufacturer for stackup where 0.1mm is 50 OHM and also for track geometry for DIFF pairs. I don't normally calculate track impedance as from my experience PCB manufacturer will change it anyway. See my posts on this subject at Welldone Blog: How to design PCB stackup, PCB impedance calculator – Single ended / Differential pair
You are a great inspiration for me. I also do design and layout, but not anything close to what you do. I also have to do DDR2 with FPGA/DSP and I will definately use this as a guide, along with the manufacturer guidelines. Thank you so much.
I would use the Interactive Length tuning function for each part of the bus routing. First from the CPU to the vias, then from the vias to each memory chip. Interesting video.
@elektroniskorg I did try the Interactive length tuning, but it didn't work very well. I didn't find a way how to specify a rule for segment length matching.
@matarofe You are right, but maybe you could try to route each segment alone. That way you can keep signal lengths equal within that segment, and when you are done you can copy and delete it. Then it shows up in the clipboard panel on the right. Do this for each segment, and paste them back when you are done.
Was the design working well after PCB manufacturing? No problems? Great video! I suppose You did use length matching tool for diff. pairs?
soclt 1 month ago
@soclt Thank you for leaving your comment. The design works very well - no problems, no issues. I still use the technique, just a little bit improved - see my latest Altium Designer - DDR2 / DDR3 Length Matching video. And yes, I did length match diff pairs.
matarofe 1 month ago
@matarofe Great! Did You also do any impedance calculations or simulations to avoid mirrored waves? I think Altium can do that.
soclt 1 month ago
@soclt
Simulations: I have done couple of simulations before and ... from my experience, when you follow design guide rules, you don't need to simulate. I have seen some boards what passed simulation and failed in reality. On other hand, I have not seen any boards what followed design guides and failed - they all worked very well. Therefore, I believe the simulation is necessary only in cases where you can't follow design guide.
matarofe 1 month ago
@soclt
Impedance: I usually start with routing everything (except powers) by 0.1mm / 0.1mm (track width / gap). When I am approximately in middle of layout, I ask PCB manufacturer for stackup where 0.1mm is 50 OHM and also for track geometry for DIFF pairs. I don't normally calculate track impedance as from my experience PCB manufacturer will change it anyway. See my posts on this subject at Welldone Blog: How to design PCB stackup, PCB impedance calculator – Single ended / Differential pair
matarofe 1 month ago
@matarofe That's quite good manufacturer. Usually I am limited to 0.15mm and no burried or uVias, otherwise the board gets very expensive.
soclt 1 month ago
@soclt in this case use 0.15mm as a reference for 50OHM single ended impedance and ask manufacturer for stackup and DIIF pair geometry.
matarofe 1 month ago
@matarofe Hm, will try that. I am still struggling to choose either SDRAM or DDR2, since the speed is not a limiting factor for me :)
soclt 1 month ago
You are a great inspiration for me. I also do design and layout, but not anything close to what you do. I also have to do DDR2 with FPGA/DSP and I will definately use this as a guide, along with the manufacturer guidelines. Thank you so much.
yanava 10 months ago
@yanava I am glad it helps :). Thank you for your comment.
matarofe 10 months ago
I would use the Interactive Length tuning function for each part of the bus routing. First from the CPU to the vias, then from the vias to each memory chip. Interesting video.
elektroniskorg 1 year ago
@elektroniskorg I did try the Interactive length tuning, but it didn't work very well. I didn't find a way how to specify a rule for segment length matching.
matarofe 1 year ago
@matarofe You are right, but maybe you could try to route each segment alone. That way you can keep signal lengths equal within that segment, and when you are done you can copy and delete it. Then it shows up in the clipboard panel on the right. Do this for each segment, and paste them back when you are done.
elektroniskorg 1 year ago
@elektroniskorg Hi. Thank you for your responses. I see you understand Altium Designer. Is this technique described in one of your tutorial videos?
matarofe 1 year ago