Lec-4 Verilog: Part-III

[Agarwalrishabh20]

There is no break statement in case in verilog. it is implicitly done because of the nature of the digital circuits. we dont write break but virtually it exists

[Agarwalrishabh20]

not decoder.. it is demultiplexer

[teja722]

there is no Sound here , please re-upload This video

[briLLiantinis]

Extremely useful data.