FPGA MD5 Cracker - Part 2

[avnsun]

really cool man!! really cool!!....

[ivanmayantsev]

You can decipher 10-15 hashes on 5 dollars for hash for me? sens84@mail.ru

[smashthestack]

Great work and explanation dude =)

[Mushketer888]

You are genius!

I wish you good luck

[AlexandruBogdan81]

Wow !!!! awesome!! :) i have a fpga board too, stratix ii kit. do you think it will work?

[CDMCSD2]

@AlexandruBogdan81 Stratix II is pretty much 3 times faster than Cyclone 2 and

can be configured to crack AES codes, MD5 will be a joke for it.

Basically your question is like asking whether a Lamborghini Gallardio can be faster and

stronger than Mazda 3 or not.... :D

[bigboy071]

To follow up on previous mail, I took some boards at my job with Altera Stratix-II 90 (EP2S90) and after 3 month, I put up something quite interesting. I have been able to unroll 7 MD5 cores per FPGA running @ 110.16MHz. I have 2 of those boards connected to a micro-controller, and I'm able to do 1.5 billion (1.5G) keys per seconds :-) I know, some newer video cards can do it, but it's still nice knowing that those FPGA are 4 years old... Imagine what one could do with today's FPGA...

[ttim6575t2000]

awesome. if computers had souls you would be there God.

Naw, but forreal nice video 5 stars.

[bigboy071]

You could try and pipeline the operations. It would take about as long to get a hash from initial input, but after that, you get one new hash per clock cycle. You could get 50 million hash / sec (3 billion hash per minutes) :-)

[Gregorpm]

That's a great idea. However, the algorithm has 4 phases and each phase is repeated 16 times, so to implement a real pipeline I would need to have 16 independent logic units for each phase and they all would need access to the two large arrays (k and r). I don't know if this implementation would fit on the fpga. It's definitely worth a try. Another idea is to just pipeline the four different phases. I donno, I'll try over winter break =D

[Gregorpm]

Now that I think about it, each of the logics would only need a single element from the k and r array! However, the original message being hashed needs to be used throughout the algorithm, but that's not to bad. Thanks again for the suggestion.

[bigboy071]

At first view, it would seem to take 64 times more resources. However, you would need logic for 64 functions instead of 4. The constants would stay the same (64 vs 64, and less muxes on them). There would be no need for barrel shifter, only routing logic would do the shifts. Less muxes for the message. However, more registers.

I don't know, this would need a bit more thinking, and some tests to see if it's practical (and if it fit in the FPGA).

[bigboy071]

Also, on the minus side, I taught of that, you also need a lot more registers to hold the message for each stage of the pipeline. So you need something like 64 16-bytes registers (actually a bit less since at the last round, the first DWORD is needed only for the first operation of the last pass, the second DWORD hold up to the second operation of the last pass, ...). Something like 32Kbits. This could be optimized though, knowing that the test passwords are not random, but sequential...

[xtaserx]

you are a genius good job you should sell that id buy one.

[rikuwillkillu]

what kind of situations can you use this for?

[Gregorpm]

A lot of websites use MD5 hashes for user passwords.

[rikuwillkillu]

oh i see thanks for the reply im new to this stuff.

[xmlisnotaprotocol]

cool