It can be sorta tough to understand this stuff, if you don't try it out. I suggest downloading the free program Logisim and actually build something! I like the lectures by the way...
How are we likely to reduce miss rate with 4 way set associative cache? He said "Reason being that if degree of associativity is low, there are more conflicts. And therefore, some of the blocks which you may like to use later on may get thrown out"
I think what he means is, that with higher associativity you can avoid more conflicts. It's what he also said earlier. For example to reduce conflicts you could also use an 8-way associative cache. Or even fully associative. But with increasing associativity you also have an increasing complexity of the cache management.
So, reducing conflicts results in higher associativity, but results in higher complexity.
@LigGLe Thanks for taking pains to write reply, I appreciate! My question however remains unanswered (sorry), awesome if you could try answering. "How/Why" would miss-rate get reduced with associativity increase?
For example your Memory has the adresses I II III IV V VI VII VIII your cache has e.g. 4 Blocks 1 2 3 and 4.
Direct mapped means that I and V are mapped to 1, II and VI mapped to 2 and so on...
So for example if the content of adress I and V are most frequently used then the cache alway has to load the other one in Block 1. So there are a lot of cache misses.
is it associative cache, blocks can be loaded anywhere in cache -> I and V can be in cache at the same time -> less misses
it seems that this professor has not him self made this presentation. due to which the listner can understand well because ^prof seems to be confused.
It can be sorta tough to understand this stuff, if you don't try it out. I suggest downloading the free program Logisim and actually build something! I like the lectures by the way...
hellwitchify 3 months ago
marvellous way of explaing ths tough topic thank u sir
sachingangualy 5 months ago
wht is cache coherence?is this topic present in dis lecture?
Arpitgupta363 5 months ago
Good lecture all in all, Thanks IITs and IISc!!!
vedhasp 8 months ago
38:15 How often do you prefetch: "Again, its a tradeoff"
Between???
vedhasp 8 months ago
How are we likely to reduce miss rate with 4 way set associative cache? He said "Reason being that if degree of associativity is low, there are more conflicts. And therefore, some of the blocks which you may like to use later on may get thrown out"
vedhasp 8 months ago
@vedhasp This is around 16:05 FYI. Please help me understand this statement.
vedhasp 8 months ago
@vedhasp
I think what he means is, that with higher associativity you can avoid more conflicts. It's what he also said earlier. For example to reduce conflicts you could also use an 8-way associative cache. Or even fully associative. But with increasing associativity you also have an increasing complexity of the cache management.
So, reducing conflicts results in higher associativity, but results in higher complexity.
I hope it's the answer to your question
LigGLe 6 months ago
@LigGLe Thanks for taking pains to write reply, I appreciate! My question however remains unanswered (sorry), awesome if you could try answering. "How/Why" would miss-rate get reduced with associativity increase?
vedhasp 6 months ago
Comment removed
LigGLe 6 months ago
This has been flagged as spam show
@vedhasp
For example your Memory has the adresses I II III IV V VI VII VIII your cache has e.g. 4 Blocks 1 2 3 and 4.
Direct mapped means that I and V are mapped to 1, II and VI mapped to 2 and so on...
So for example if the content of adress I and V are most frequently used then the cache alway has to load the other one in Block 1. So there are a lot of cache misses.
is it associative cache, blocks can be loaded anywhere in cache -> I and V can be in cache at the same time -> less misses
LigGLe 6 months ago
thank u very much sir for uploading this video
Arif ullah khan from pakistan
ikramakhund 2 years ago
same remarkes!
mohsinamin 3 years ago
it seems that this professor has not him self made this presentation. due to which the listner can understand well because ^prof seems to be confused.
mohsinamin 3 years ago