Lecture - 20 Virtual Memory

[theraccoun]

the music at the beginning is what really pulled me in

[1sanjaygir1]

thumbs up if this is the best way of explaining stuffs.

[l1f07bscs0035]

I like the way he start lecture from zero and goes to all concepts ........moreover first telling the functionality and then telling name of that component is very efficient.....................­..........my teacher of mathematics have same teaching style.....................star­ting from zero.....why we need...... solution.....and so on

[l1f07bscs0035]

great lecture.......................­

[TheRealAnalysis]

This is great. thank you!

[TheMaryam2222]

great lecture.......thanks

[javacoder1986]

amazing lecture, thanks for clearing my virtual memory funda, thank you !!!

[ANBALAGANRAJAGOPAL]

Sir you are awesome, great, extraordinary, i would have become a scientist if i had professor like you during my college.

A small correction sir, using 20 address lines we can address 1 MB not 1 GB, but I know this would have happened with out intension.

[pdnoto]

I have not seen a person cover the basics in a better way. Awesome !

thanks to nptelhrd !!

[comcom8229]

The advantage of cache (speed)is getting evaporated,if the address is a feed to cache,and if its in there v can avoid the memory access needed to do a look up in the page table.

[jas03023]

@comcom8229: There will always be a one compulsory cache misses the first time the memory is accessed. The true benefit of cache is realized if the memory is accessed again. TLB miss is expensive and would require relocation, how ever there are techniques that reduce this probability.

[comcom8229]

what i mean is the purpose of cache is getting lost.i believe this what happens if there is a TLB MISS, logical address->MMU->physical address-->TLB miss-->Cachemiss->RAM--->page fault-->Secondary storage--->update in page table .This sequence sounds perfect to me,i would be happy to know if i had miss understood something.

[comcom8229]

Everthing is perfect except one thing which iam not sure,that is when there is a TLB miss.He specifies it does a Page table Read that is in main memory(Page table is in main meory) and if the page is there,y dont v fetch from there itself(since all the contents of cache should be there in main memory but vice versa is not true) y do u want to go to cache and then fetch it. so if u do so and that is not present in cache,he then says to go and look again in main memory??

[tryedu2000]

you are awesome.. ur lectures would be on my site soon ..

tryedu dot net /fm/

[v0ks1]

i love india

[mustafai1984]

very well explained .... nice post :)

[gauravzerogravity]

indians rulez in education

[daviangel]

Now I actually have an idea of what the Phenom TBL bug was about! Before Phenom's original release, a flaw was discovered in the translation lookaside buffer (TLB) that could cause a system lock-up in rare circumstances.

[daviangel]

Very good with plenty of worked out examples!

[elchavo87]

Thanks for the lecture.

[petersin71395]

i dont understand anything lol but great indepth video

[antonythanesh]

Superb Sir.. It is really giving insight of Virtual memory...Awesome

[akcelebrity1]

it is a good and very useful video lecture.i thank iitm for providing such a useful resource.

[ntsdsl]

Thanks a Lot ! Great Vids :D .. Very Helpful..Long Live the Professor :D

[inline853]

it is a good vid. thanks!!

[nramesh83]

great video...covers the basics very comprehensively