Lec-2 Verilog: Part-I

[PoliteCitizen]

dirty indian scum

[Agarwalrishabh20]

He made some major mistakes which will shake the basics of verilog. Never expected this from an iit lecturer

[merlin8184]

Massively helpful, thanks for the upload!

[taatiko1]

why was it muted?

[jaligam1]

very useful

[jaligam1]

very useful for vlsi aspiring students



[overfarhan]

thanks helper.sory for late reply.busy with exxam

[overfarhan]

no sound



[joemck85]

@overfarhan Listen to the RIGHT audio channel. Or use a mono-to-stereo adapter to hear it on both sides like I'm doing.

[KVirus]

I wish my lecturer was that good !!

[vedhasp]

Good lectures these are, thanks a lot!!!! Just one correction at 36:41 though... As I understand, by default data type is wire, not reg.

[abiabirami60]

@vedhasp Net is the default data type ..

[MrStones38]

absouletly u right

[Flyer85H]

the bip at the start almost killed me...

[ansarimoni]

@Flyer85H dont lie



[shammy539]

Great introduction to verilog  !