VLSI / FPGA Design Demo (DDR Controller)

[heeroyui1777]

First, Great video!!!.

Second,

I need help please!

Im building a FPGA board but im need to know if i REALLY NEED put termination resistors on all DDR SDRAM wires. Im designing targeting to Altera Cyclone III (PQFP package)

[cfrancof]

I need help too. I dont know how to manage the .Vhd files how did you conect them can you tell me please?

[cfrancof]

Hi. I have a lot of problems too. Please can you help me ?

I have generated the testbench mode but the UCF file that generates is wrong and if i try to change it , shows me error. please help

[alexgiul1982]

Great!! Drr is very difficult to controll!!

Hi I'm interested in ddr controller for my spartan 3e kit too, can I have your email?

Do you have any documentation about your project?

[jerrygwu]

This is my student's presentation.

If you have any question regarding to DDR,

I'm more than happy to share my experience with you.

[alexgiul1982]

Hi my problem is that I have generated the core with mig 2.0 but I don't understand how use it...for example I would write and after read some byte and check if they are the same..

[jerrygwu]

Hi,

What happen when you write after read ?

They should be the same unless you have BE.

Another way to confirm the DDR protocal is you can go to MIRCRO's website to read their document. Their documentation is very good.

Thanks

Jerry.

[cfrancof]

please jerry help me.

I don't know how to conect the .vhd files on my project. please help me