Videos from Doulos

by aijnsleij

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VHDL versus SystemVerilog

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by aijnsleij 4 months ago

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16:03 First Steps with UVM Part 2 aijnsleij 30 views 5 days ago John Aynsley from Doulos presents a simple, complete SystemVerilog UVM source code example (which you can download), explaining what is happening and highlighting best prac...
24:01 First Steps with UVM Part 1 aijnsleij 113 views 1 week ago John Aynsley from Doulos presents a simple, complete SystemVerilog UVM source code example (which you can download), explaining what is happening and highlighting best prac...
20:10 SystemVerilog for Hardware Synthesis aijnsleij 565 views 3 months ago John Aynsley from Doulos gives a detailed explanation of how to use the synthesis-friendly features of the SystemVerilog language
9:58 How Much SystemVerilog Training Do You Need? aijnsleij 541 views 4 months ago John Aynsley from Doulos answers the question "How Much SystemVerilog Training Do You Need?" by explaining Doulos' SystemVerilog training portfolio, how to choose the right...
10:29 VHDL versus SystemVerilog aijnsleij 940 views 4 months ago What is the difference between VHDL and SystemVerilog? John Aynsley from Doulos compares these two language standards
16:33 Using your C Compiler to Exploit NEON aijnsleij 505 views 6 months ago Dave Cabanis from Doulos explains how to exploit the NEON coprocessor unit found in the ARM Cortex A processor family from your C code.
13:06 Using the Cortex-M3/M4 Flash Patch Breakpoint Unit aijnsleij 135 views 7 months ago David Cabanis from Doulos explains how to use the flash patch breakpoint unit of the ARM Cortex-M3 and M4 processors.
14:47 What's New with VHDL aijnsleij 3,622 views 1 year ago John Aynsley from Doulos describes some useful, practical features from the VHDL 2008 language standard that are supported by several simulation tool vendors.
10:00 Introduction to UVM - The Universal Verification Methodology for SystemVerilog aijnsleij 2,393 views 1 year ago John Aynsley from Doulos gives a brief overview of UVM, the Universal Verification Methodology for functional verification using SystemVerilog.
9:08 Using OVM within SystemC for Verification aijnsleij 1,528 views 2 years ago Describes OVM-SC, the implementation of the Open Verification Methodology within SystemC, which is part of the open-source OVM-ML (Mixed Language) library donated to the OV...

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About Videos from Doulos

by aijnsleij

Latest Activity

May 22, 2012

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Jan 24, 2009

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53

Country

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